Topic
chip design
Technology IBM's NanoStack chip packs 100 billion transistors in sub-1nm breakthrough for enterprise AI and data centres
IBM has announced a new chip architecture called NanoStack that crams 100 billion transistors onto a fingernail-sized surface at roughly 0.7nm, the first known sub-1nm design. In tests, the prototype delivered 50% better performance and 70% energy efficiency versus IBM's 2nm chip. The technology, still years from production, relies on stacking transistor sheets vertically to extend Moore's Law.
LLM4RTL System Boosts RTL Code Generation with Tool-Assisted Pipeline
A new research paper proposes LLM4RTL, a tool-assisted large language model system for RTL code generation. The system uses a judge-renew-check-renew-check (JRCRC) pipeline to filter and refine training datasets, and incorporates pre-processing tools to address LLM weaknesses in rule-based reasoning. LLM4RTL achieves significant performance gains on the VerilogEval benchmark, rivaling GPT-4O with a smaller model.