Enterprise technology leaders relying on powerful computing for AI, data analytics, and supply chain automation should watch a new chip architecture from IBM that crams an unprecedented number of transistors onto a surface the size of a fingernail. According to BBC Business, IBM's NanoStack design achieves roughly 0.7 nanometres — the first known chip technology below 1nm — and packs almost 100 billion transistors. In tests, the prototype performed 50% better and was 70% more energy efficient than IBM's own 2nm chip, the company said.
The breakthrough: sub-1nm and 100 billion transistors
For decades the semiconductor industry has followed Moore's Law, doubling transistor counts roughly every two years. But with billions of transistors already on chips, sustaining that pace has become harder. IBM's answer, reported by BBC Business, is a 3D architecture called NanoStack that layers sheets of transistors on top of each other rather than placing them flat. Jay Gambetta, director of IBM Research and IBM Fellow, described the development as a "landmark moment" for the future of chips. "With our new NanoStack architecture, we're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency," he said.
The table below summarises the performance gains IBM reported:
| Metric | IBM 2nm chip (2021) | IBM sub-1nm NanoStack prototype | Improvement |
|---|---|---|---|
| Performance | Baseline | 50% higher | +50% |
| Energy efficiency | Baseline | 70% higher | +70% |
| Transistor count | Not disclosed | ~100 billion on fingernail size | Dense stacking |
How NanoStack works: stacking transistors like a skyscraper
Transistors are the building blocks of silicon chips, powering everything from smartphones to data centres. IBM's approach is to layer sheets of transistors vertically. Professor Alan Woodward, a computer scientist at Surrey University, compared it with building a big block of flats rather than houses in a city. "IBM's NanoStack is like proposing a 100-story skyscraper," he told BBC Business. In his view, rivals such as Samsung and Intel are closer to 30-50 story buildings with their own 3D chip work.
The challenges: heat and switching reliability
Three-dimensional chip design faces two major physical hurdles: heat and transistor switching. Heat rises as transistors work, and when the layers between them are too thin, they may fail to switch off when required, causing the chip to malfunction. "I think it's fair to say IBM's proposals are the most ambitious," Professor Woodward added.
Implications for enterprise technology and supply chain
While IBM's NanoStack is still years away from production, its potential impact on enterprise computing is significant. The chips are designed for the powerful computers in data centres that process streaming, online banking, and generative AI workloads — all of which underpin modern supply chain analytics, logistics optimisation, and trade finance automation. A 50% performance boost and 70% energy reduction could translate into lower cloud costs and faster AI inference for customs classification, demand forecasting, and route planning. For CTOs evaluating long-term technology roadmaps, NanoStack signals a future where data centre chips can deliver more compute per watt, directly enabling more sophisticated trade technology platforms without proportionally increasing energy bills. However, as BBC Business notes, it will be several years before the chip tech could be ready for production.
Sources:
