Modern processors spend the majority of their area and energy on addressing — moving operands to and from registers and caches, and managing tags, ports, miss queues, and bypass networks. According to a paper published on arXiv and authored by Bergach and Mohamed Amine, a new architecture called MADAR (an address-free processor) deletes this machinery by abolishing the address altogether.
How MADAR Works
In MADAR, all state circulates in rings of slots that advance one position per clock cycle. Instructions and data ride in the same slots. A value is named by its place in an orbit — a "rep" coordinate — not by an address. A fixed station computes when a circulating instruction sweeps past its operands, on a schedule set at compile time. A hierarchy of rings of increasing period replaces the cache hierarchy, with movement between rings scheduled rather than triggered by a cache miss.
The paper states: "No prior circulating-store, dataflow, or statically scheduled machine combines all four of these." The authors validate the execution model with a cycle-accurate register-transfer-level implementation, and show it is compilable — a constructive scheduler emits programs cross-checked against the implementation. A first-order energy model prices the design.
Impact on AI Acceleration
The payoff is clearest for AI acceleration. The multiply-accumulate operation at the heart of every matrix multiply and convolution compiles to a streaming form whose energy per operation stays flat as the reduction grows. Operand reuse — what makes matrix multiplication efficient — is carried by the ring-period hierarchy. As the paper notes, this is "the memory hierarchy doing by rotation what a cache does by tags."
Comparison: Traditional vs. MADAR
| Feature | Traditional Processor | MADAR Processor |
|---|---|---|
| Addressing | Heavy hardware for tags, ports, bypass networks | None — values named by orbit coordinate |
| Memory hierarchy | Cache with miss-triggered movement | Ring hierarchy with scheduled movement |
| AI workload energy | Energy scales with operand movement | Energy per operation remains flat |
| Schedule | Dynamic (out-of-order) | Static (compile-time) |
Broader Implications
MADAR is a new design point for any computation whose data movement is known before the program runs. This includes many enterprise workloads such as large-scale data analytics, signal processing, and scientific computing, where data access patterns are predictable.
For chief technology officers and supply chain technology managers evaluating next-generation hardware, MADAR represents a potential shift: processors that dedicate far less silicon and power to data movement could dramatically lower the total cost of ownership for AI inference and training clusters. While the architecture is still in academic validation, the principles could influence future commercial designs from major chipmakers or specialised AI accelerators.
The paper concludes that MADAR is "a new design point for any computation whose data movement is known before the program runs."
